There are many applications in electronics that require a capacitive type load to be driven with a square wave voltage. This capacitance may be for example, the input gate capacitance of a power MOSFET, the input gate capacitance of CMOS logic gates, the input or clock lines of VLSI digital circuits, memory address lines and the row/column select lines of a LCD matrix. The conventional manner of driving a capacitance with a square wave of variable frequency and duty cycle is illustrated in FIG. 1 (prior art). The conventional capacitance-driver (1) consists of two switches (S1 and S2) connected in series in a half-bridge configuration. The junction between the two switches (i.e. the midpoint) drives the capacitance directly. The switches are usually implemented using semiconductor devices such as FETs or bipolar transistors. The capacitance is charged through switch S1 to the supply voltage Vs, and discharged through S2 to ground. The conventional driver can operate with a variable duty cycle from DC—to its maximum working frequency, and it can keep the voltage across the capacitance in one state (high or low) indefinitely. However, the conventional driver (1) of FIG. 1 suffers from some significant disadvantages, the main one being the inherent power loss or power dissipation associated with this method.
The capacitive power dissipation of the conventional driver (1) can be calculated as follows. If the capacitance, C, is being driven by a square wave of frequency, fs (referred to as the switching frequency), and a peak to peak swing equal to Vs, then the power dissipated in the conventional driver (1) is given by the equationPD=C Vs2fs  (1)
If the capacitance is non-linear then the power dissipated is given byPD=QgVsfs  (2)where Qg is the total amount of charge need to charge the capacitance from ground to Vs. It can be seen that the power dissipated is independent of the on-resistance of the switches used to charge and discharge the capacitance i.e. lowering the on-resistance will have no effect on the amount of power dissipated. The power dissipated is proportional to the switching frequency and can become a very significant factor with increasing switching frequencies, and/or large capacitances, and/or large voltages. An example of this capacitive power dissipation is the fact that it is main cause of power loss in most current computer processors.
The conventional driver (1) also suffers from other disadvantages when used in applications such as MOSFET gate drivers or capacitive line drivers. These include;                1. The original square wave drive signal is usually generated by logic circuits, and hence will be a logic level signal (e.g. 5V or 3.3V). However, many applications (but not all) require the voltage across the capacitor to be higher than this. For example, a power MOSFET requires the gate capacitance to be charged up 10V or more. Hence the conventional driver must be provided with an independent higher supply voltage of 10V or more (shown as Vs in FIG. 1.). In addition to the higher supply voltage, a means of level shifting the original logic level drive signal must then also be provided to enable the high side switch S1 to be driven.        2. During the switching transitions (as S1 turns off and S2 turns on or vice-versa), some cross-conduction through S1 and S2 arises due to the fact that practical switching devices will have non-zero switching times. This is another cause of power loss in the conventional driver (1) and this loss again increases with increasing switching frequency.        3. Parasitic (leakage) inductance in the charging or discharging path can cause undesired effects such as ringing.        
The following patents and publications have all attempted to address the above problems to some degree with various solutions.
PatentsUS33775411968FarkusUS4873460October 1989RippelUS4967109October 1990SteigerwaldUS5010261April 1991SteigerwaldUS5804943September 1998Kollman et al.GB1327406October 1970MilbergerUS36364761972MilbergerUS37602851973Milberger et al.US5473526December 1995Svensson et al.US5514921May 1996SteigerwaldUS5537021July 1996Weinberg et al.US5559478September 1996Athas et al.US41077571978MasudaUS5134320June 1992PerusseUS5264736November 1993JacobsonUS5276357January 1994CripeUS58523581998EshaniOther Publications    W. Tabisz, P. Gradezki, F. C. Lee. “Zero-Voltage-Switch Quasi-Resonant buck and flyback Converters—Experimental results at 10 MHz.” IEEE Power Electronics Speacialists Conference Record, 1987, pp. 404-413.    Dragan Maksimovic, “A MOS Gate Drive With Resonant Transitions.” 22nd Annual IEEE Power Electronics Specialists Conference (PESC), Jun. 23-27, 1991, pp. 527-532.    H. L. N. Wiegman, “A Resonant Pulse Gate Drive for High Frequency Applications,” General Electric Corporate Research & Development, IEEE 0-7803-0485, Mar. 3, 1992, pp. 738-743.
These circuits are not without their disadvantages and suffer from some or all of the following limitations. The circuits are usually limited to driving the capacitance between two set voltage levels which depend on the supply voltage provided and may still require a higher supply voltage. Some of the circuits require bi-directional switches, and hence will have the practical difficulties and limitations associated with bi-directional switches. Some of the circuits require complex timing circuitry that has to be designed for a particular value of capacitance and inductance and hence they will be limited in their use to a particular application.